ASIC Design Projects

 

The rDPA Control Design is a 1.0mm CMOS Standard Cell design with embedded memory. The chip size is 26,5mm² and the design contains 58140 equivalent transistors. The project started with the concept of the design and included all design steps (such as e.g. schematic entry, design synthesis using Verilog, placement and routing and design simulation) till testing of the final silicon. A project description is available in <PDF> format (German text).

The rDPA chip is a 0,7 mm CMOS Standard Cell design with embedded memories and datapaths. The chip size is 144mm² and the design contains 373033 equivalent transistors. The project started with the concept of the design and included all design steps (such as e.g. schematic entry, design synthesis using Verilog, placement and routing and design simulation) till tape out. The rDPA chip is a hierarchical design and consists of 9 identical DPUs. Each DPU contains memory cells and a datapath block. Thus it can be seen as an early form of IP-based design. A project description is available in <PDF> format (German text).