| High Performance Memory Communication Architectures for Coarse-grained Reconfigurable Computing Systems |
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| Ph.D. Thesis | |
| Table of Contents |
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Address Generation Concept 91-94
Address Generator 37-72, 263-280
Central User Administration 228
Classification of Scan Pattern 96-107
Coarse-grained Reconfigurable 5-24
Compare, Select, Store Operation 57
Concurrent Data Access 153, 263
Δ A 99, 109, 269
KressArray Implementation 125-218
Data Transmission Protocol 289
Δ B 99, 109, 266
Development Framework 3, 225-240
Δ L 99, 109, 266
DP-FPGA see Datapath-FPGA
Handle Position Generator 94, 264-270
Handle Position Generator (MoM-3) 53
Hardware Level Optimizations 153-174
High Level Language Interface 229, 234
HSP45240 see Intersil Address Sequencer
ILP see Instruction Level Parallelism
Image Processing 56, 116, 184, 207-218
Inner Scan Line Loop Unrolling 162
Instruction Level Parallelism 155
MAG see Memory Address Generator
Map-oriented Machine 2 44-47, 83
Map-oriented Machine 3 51-57, 84-86
Map-oriented Machine with Parallel Data Access 159, 183, 226, 253
Bank Interleave Addressing Scheme 159
MCU see move control unit
MDRAM 26, 158, 253-260, 262, 275, 286
Activation of Multiple Banks 259
Memory Access Simulator 231, 236
Memory Communication Models 123-125
Memory Interface Performance 2
Memory Mapper 151-152, 263, 273-275
MoM-PDA see Map-oriented Machine with Parallel Data Access
MoPL 98, 102, 104, 106, 111, 121, 199, 234
Reconfigurable Cell Architecture 19
Multi-level Scan Pattern Generation 264
Parallel Memory Banks 75, 148-152, 153, 189, 269, 274
Perfect Data Access Scheduling 175
rALU see reconfigurable ALU
Rambus see RDRAM
rAP see reconfigurable ALU Port
Scan Window Generator 94, 124, 128, 269-272, 277
Scan Window Overlapping 155, 190
Pseudo Code Description of 101
Speed-up 153, 157, 159, 192, 201
Stack-based Scan Pattern Generation 281
Stream Mapper Operator With Control 209
Structured Memory Access Machine 38-41
Surrounding Data Memory 124-125