List of Tables

Table 2-1: Summary of the technical details of the different coarse-grained reconfigurable architectures. 23

Table 3-1: Summary of the technical details of the different DRAM types. 27

Table 4-1: The presented address generators at a glance. 71

Table 6-1: Scan pattern classes. 108

Table 6-2: Parameter assignment for different stepper implementations. 109

Table 6-3: Graphical representation of DPUs used in this thesis. 123

Table 7-1: Speed-up figures ( speeduppar ) for concurrent data accesses. 154

Table 7-2: Speed-up figures ( speedupoverlap ) of the scan window overlap optimization for some scan window examples. 156

Table 7-3: Speed-up figures for memory accesses in burst mode, calculated under application of equation 7-8. 159

Table 7-4: Results of the data map transformation for the application example in figure 7-22 at page 172. 173

Table C-1: MDRAM commands and their semantics and opcodes. 256

Table D-1: Technical details of the Altera FLEX 10k100 CPLD. 285

Table D-2: Data sequencer implementation details. 286

Table D-3: Data sequencer details. 286

Table D-4: Scan window generator details. 287